Wafer Scale Integration is Underway
For all the talk of extrasensory artificial intelligence (AI), trans-human electric planes, erbium-doped brain implants, cosmic exploration, quantum computing, and “n” G wireless, the most important invention of the next era is likely to be… are you ready? The integrated circuit (IC).
The integrated circuit was already invented in the late 1950s, twice actually. First, Jack Kilby at Texas Instruments in Dallas concocted an integrated circuit — a “flip-flop” memory cell — in a clumsy un-manufactural form with gold wires looping over the surface of a germanium substrate. For this, he won the Nobel Prize for Physics in 2000.
Then, weeks after Kilby in 1959, Robert Noyce at Fairchild Semiconductor offered the real deal, a “planar” (flat) IC on silicon with implanted wires that could be mass-manufactured in volume in industrial ovens by his colleagues Gordon Moore and Jean Hoerni.
The first real silicon integrated circuit, Noyce’s monolithic IC design laid the technical foundations for the global microchip industry that has been the key to world economic growth ever since. Because of this, he won great wealth and prestige at Intel Corporation and a definitive biographical essay by Tom Wolfe.
So how then can I say that the key invention of the next era is an integrated circuit? I could define it more precisely as a silicon integrated circuit board.
The goal of the IC was to put entire electronic circuits on silicon chips, thus drastically reducing the size and increasing the speed of the systems. However, sixty years later, some 95 percent of the area and thus the delay or latency in electronics is still consumed not by the silicon chips that perform the functions but by printed circuit boards (PCBs).
Usually made of fiberglass and epoxy or various plastics, these expanses of wired wasteland power up the chips and interconnect their plastic or ceramic packages. These complexities reduce the number of connections per square centimeter of the chip area down to some 400. At the same time, the distance that signals have to travel increases by orders of magnitude.
This posed an issue…
Rent’s Rule Stalls Out
This problem has long been defined by Rent’s Rule, ordaining that the number of connectors to a chip increase only by the logarithm of the number of transistors on the chip. From plastic cards in smartphones to racks in data centers, the problem is solved by enlarging the wires and passive devices and spreading them out across PCBs. This process consumes most of the space and time used in electronics.
Since current chips can contain as many as 16 or more billion transistors, rent’s rule means one connection for every 40 million devices. A great electronics bottleneck, this rule has stalled the improvement in the clock rates of ICs at some three or four billion cycles per second (Gigahertz).
The intrinsic clock-rates of the transistors is many times faster. At the same time, this problem limits the form factors of electronic gear to hundreds of times more volume and weight than is theoretically possible on the silicon die themselves (die is plural for die).
As Puneet Gupta and Subramanian S. Iyer write in October’s issue of IEEE Spectrum:
“We believe that a better solution is to get rid of packages and PCBs altogether and instead bond the chips onto a relatively thick (500 microns to one millimeter) silicon wafer. Processors, memory dies [unpackaged chips], analog and radiofrequency [RF] chiplets, voltage regulator modules, and even passive components such as inductors and capacitors can be bonded directly to the silicon.”
Called wafer-scale integration, it means distributing the chip die not across a printed circuit board but the 12-inch-wide silicon wafer they are fabricated on. This idea has entranced many of the greatest minds in electronics for decades.
Eugene Amdahl of IBM and Amdahl was a pioneer. But the more devices integrated on a single wafer the more the defects and the lower the yields of the manufacturing process. At the same time, wafer-scale integration increases the problem of conditioning and delivering power to the circuits and implementing passive elements such as capacitors, resistors, inductors, and busses.
Showing the way to create such wafer-scale silicon printed circuit boards — integrated boards for short — is a former researcher at Argonne National Laboratories named Pierre de Rochemont.
Chiplets are the Key
While much of the industry has been addressing these challenges with software, de Rochemont is a materials scientist. He believes that the secret to the future integrated circuit on silicon will be new materials that allow the miniaturization of passive elements that can perform with the precision of macroscale devices.
De Rochemont is in stealth mode, so I cannot reveal any details. But he has several competitors addressing the same wafer-scale challenges. Involving room temperature superconductivity and other exotic phenomena, the integrated circuit board has long seemed a bridge too far. Like most major advances, it will require a series of smaller steps.
The first step is already evident across the industry. Rather than creating giant systems-on-a-chip that require high levels of redundancy and error correction and reduced manufacturing yields, the industry is breaking systems down into chiplets.
Reusable blocks of intellectual property, these bare modular devices are then laid out and interconnected on silicon substrates. An array of interconnected chiplets comprise a system on a chip. Chiplets have been crucial to industry-leading technologies at AMD and NVIDIA and are key to effective AI and machine learning advances.
Chiplets will be key to the new integrated circuit boards on silicon.
The rewards of this new integrated circuit will be immense, extending Moore’s Law — the doubling of device densities every two years or so — and taming what are now the vast open spaces of printed circuit boards.
Wafer-scale integration will come at last.
This breakthrough will release trillions of dollars’ worth of new efficiencies across the entire economy. It will open a new frontier for Nanosystems. It is the next revolution in electronics and it will soon offer major opportunities for savvy investors.
That’s the big story for 2020 and we will be following it closely.
If you’d like to follow the other big stories for the upcoming year, I discuss these themes in great detail in my flagship newsletter, The George Gilder Report.
Perfect timing, too — I just released the October issue which has a brand-new recommendation.
Editor, Gilder’s Daily Prophecy