The Source of My Store Width Paradigm
“Pipedream,” he says.
In my Information Theory of Economics, economic growth is learning. It depends on the possibility of failure and correction.
Here at the Gilder’s Daily Prophecy we are always ready to learn.
My prophecy on the invention of a new integrated circuit (IC) — an integrated circuit board — evoked a “pipedream” dismissal from John Schroeter, my Moonshot paragon and resident microchip expert.
In the process of explaining to me why some of my predictions of wafer scale integration are hallucinogenic, he expounded in beautiful detail the source of my “store width paradigm.”
A multi-patented author of a textbook on How to Design an ASIC, among other learned books, Schroeter wrote:
In terms of where the industry really is on it now and for the foreseeable future, I believe [wafer scale integration or WSI] will remain a pipedream.
That’s because WSI won’t be economically practical. The biggest challenge these days is power consumption. And the highest cost operation in compute is data movement…
To illustrate the gross inefficiencies of moving data in modern computing systems, consider the analogy of driving a car from San Francisco to New York to buy a $1 candy bar. Briefly, this involves 3,000 miles @ 25 mpg = 120 gallons @ $3/gallon = $360. That’s a ratio of 360:1, which is, of course, an absurdity. But this fool’s errand is actually FAR more efficient than moving a number from RAM to the CPU to perform, for example, a floating point computation, where the ratio (in relative picojoules) is >1,000:1!
Moving data is indeed very expensive in terms of computing resources. In fact, data movement presents the most daunting engineering and computer architecture challenge.
There is an ever-widening gap between processor and memory performance, and that gap will continue to widen as the aggregate rate of computation on a single chip will continue to outpace main-memory capacity and performance improvements (the amount of time it typically takes to access data from memory is more than 100 times the single cycle time of the CPU core).
In addition to performance concerns, the movement of data between cores and between the processor and memory chips consumes a substantial portion of a system’s total power budget.
Hence, to keep memory from severely limiting system power and performance, applications must increase locality.
In other words, the mapping of data and computation should minimize the distance that data must travel — or better yet, eliminate movement entirely where possible. This is why one of the most significant areas being worked on now is performing compute operations inside the memory itself (processing-in-memory).
In the meantime, everyone is going to great lengths to reduce the distance data must travel. Presently, silicon interposers (2.5D) are the incumbent technology of choice.
Here we see stacked die memory (high-bandwidth memory, or HBM, or Micron’s Hybrid Memory Cube) and, say, a Xilinx FPGA, packaged together on the same substrate.
In the HMC, for example, you have a stack of four DDR [double data rate] memory chips sitting atop a logic layer that performs the control functions. And they are connected with through-silicon vias – an amazing assembly technology that runs die-to-die interconnect right through the die.
So we’re seeing lots of development in 3D and 2.5D of increasing complexity.
Thank you, John Schroeter, for your excellent exposition of the argument for my store width paradigm.
The other problems I see with WSI are yield (costliest scrap imaginable), the junction temperatures of the various components, mechanical integrity, scalability… You get the idea.
WSI will always be exotic. But chiplets have a long life with interesting innovations, for example, surrounding a compute element (CPU, FPGA, AI ASIC, etc.) with, say 8 GDDR6 memory die, all planar, on a common substrate.
Well, quod erat demonstrandum (QED).
Within my capacious definition, “wafer scale” would include such a combination of chiplets and memory on a single substrate.
Why couldn’t it be a silicon substrate? A silicon substrate is not a circuit board.
I know that doesn’t fit the usual definition of wafer scale integration, which implies a single integrated process of fabrication.
But any movement beyond circuit boards onto silicon substrates can advance toward a revolution in electronics.
Editor, Gilder’s Daily Prophecy